These timing fields are automatically calculated based on the operating point and speed bin. User intervention is not typically required.
LPDDR5 SDRAM
- Read Latency (nCK)
- Sets the number of clock cycles from a read command to the first valid data output on the DQ bus.
- Write Latency (nCK)
- Sets the number of clock cycles from a write command to the point at which the controller drives valid data onto the DQ bus.
DDR5 SDRAM:
- CAS Latency (nCK)
- Sets the column access strobe latency, defining the number of clock cycles from a read command to the first valid data output.
- CAS Write Latency (nCK)
- Sets the number of clock cycles from a write command to valid data input at the DRAM device.