Memory Initialization and Configuration - Memory Initialization and Configuration - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

Memory initialization sequence is split into two steps. The memory initialization step which is done before command/address trainings and the memory configuration step which is done after the trainings. Memory initialization involves the power up sequence and multi-purpose commands to program the required DRAM settings. This is to enable performing the required command/address trainings. After the command/address trainings are completed, the interface is ready for mode register configuration which is part of the Memory configuration step. Memory initialization and configuration is performed by the MicroBlaze™ by using the pattern generator logic. MicroBlaze firmware needs some of the user configuration values (signal integrity power integrity (SIPI) related values such as RTT*, Vref, Drive strength, etc.) as a part of the calibration header files with which the memory initialization and configuration values are derived and the sequence is performed accordingly.