Memory Controllers - DDR5/LPDDR5 - Memory Controllers - DDR5/LPDDR5 - 1.0 English

Figure 1. AXI NoC2 General Tab — Memory Controllers section (Components topology; DDR5 or LPDDR5 selectable in DDR Basic tab)

Figure 2. AXI NoC2 General Tab — Memory Controllers section (DIMMs topology; DDR5 SDRAM forced)

Device Type

Selects the top-level memory device topology. This is the primary selector that determines which memory interface configuration and associated GUI options become available.

None: No memory controller is instantiated.
Components: Configures the controller for discrete memory components. When you select Components, you can set the Controller Type in the DDRMC5 Configuration dialog box to either LPDDR5 SDRAM or DDR5 SDRAM. This allows you to choose the memory protocol in the DDR Basic tab.
DIMMs: Configures the controller for DDR5 SDRAM DIMM topologies. Selecting DIMMs forces the DDRMC5 Controller Type to DDR5 SDRAM and requires a minimum of two memory controllers (refer to the following section 'Memory Controller').

Memory Controller

Sets the number and arrangement of DDRMC5 memory controller instances.

Single Memory Controller: One controller instance. Available when Device Type is set to Components. Not available when Device Type is set to DIMMs.
x2 Interleaved Memory Controllers: Two interleaved controller instances. This is the required minimum when Device Type is set to DIMMs. Also available for Components.
x4 Interleaved Memory Controllers: Four interleaved controller instances. Available for both Components and DIMMs topologies.

Note: When Device Type is set to DIMMs, x2 Interleaved Memory Controllers is the minimum valid selection. Attempting to set a single memory controller with the DIMMs topology results in a validation error.

Number of Controller Channels

Displays the number of memory channels per memory controller instance. This field is set automatically based on the selected topology and Controller Type. The field is not directly user-configurable in this dialog box.

For Components (LPDDR5) topology: Set to Dual when a 2x16 configuration is selected. Set to Single when a 1x16 or 1x32 configuration is selected.
For Components (DDR5) topology: Set to Single.
For DIMMs (DDR5) topology: Set to Single (grayed out).

Number of Memory Controller Ports

Sets the number of AXI ports used to drive each memory controller instance.

1: Single AXI port per memory controller.
2: Two AXI ports per memory controller, providing additional bandwidth or enabling traffic isolation between port consumers.

The behavior of this field and the interleave status text depend on the Memory Controller count and channel configuration.

Table 1. Memory Controller Port Selection and Interleave Status
Memory Controller	Channels	Ports	Interleave Status Text
Single MC	Single	1 or 2 (selectable)	(none)
Single MC	Dual (LPDDR5 2x16)	2 (forced)	"2-way Interleave with Channel Interleaving Enabled"
x2 Interleaved	Single	1 or 2 (selectable)	(none)
x2 Interleaved	Dual (LPDDR5 2x16)	2 (forced)	"4-way Interleave with Channel Interleaving Enabled"
DIMMs (x2 Interleaved)	Single (grayed out)	1 or 2 (selectable)	(none)

Note: The ports are forced to 2 only when Number of Controller Channels is Dual (LPDDR5 2x16 configuration). The N-way interleave count reflects the total number of independent memory ports across all controller instances (ports × MCs).

Interleave Size in Bytes

Sets the address interleave granularity across multiple memory controllers or channels.

Valid values: 0 (disabled), 64, 128, 256, 512, 1024, 2048, 4096 bytes.
Default: 128 bytes

The Interleave Size field is grayed out when there is a single memory controller with a single channel configuration. This is because there are no multiple targets to interleave across. In all other configurations (multiple memory controllers or dual channel), you can select the field.

DDR Address Region 0 / DDR Address Region 1

Sets the address region assignment for each DDR channel. Each region maps a contiguous physical address range to a memory controller channel. DDR Address Region 0 defaults to DDR_CH0_LEGACY; DDR Address Region 1 defaults to NONE.

The available address regions and their physical address ranges are as follows:

DDR_CH0_LEGACY: Start: 0x0000_0000_0000, End: 0x0000_7FFF_FFFF (2 GB) The lower 2 GB of 32-bit legacy DDR address space.
DDR_CH0_MED: Start: 0x0008_0000_0000, End: 0x000F_FFFF_FFFF (32 GB)
DDR_CH0_HIGH_0: Start: 0x00C0_0000_0000, End: 0x00FF_FFFF_FFFF (256 GB)
DDR_CH0_HIGH_1: Start: 0x0100_0000_0000, End: 0x01B7_7FFF_FFFF (734 GB)
DDR_CH1: Start: 0x0500_0000_0000, End: 0x057F_FFFF_FFFF (512 GB)
DDR_CH1A: Start: 0x0580_0000_0000, End: 0x05FF_FFFF_FFFF (512 GB)
DDR_CH2: Start: 0x0600_0000_0000, End: 0x067F_FFFF_FFFF (512 GB)
DDR_CH2A: Start: 0x0680_0000_0000, End: 0x06FF_FFFF_FFFF (512 GB)
DDR_CH3: Start: 0x0700_0000_0000, End: 0x077F_FFFF_FFFF (512 GB)
DDR_CH3A: Start: 0x0780_0000_0000, End: 0x07FF_FFFF_FFFF (512 GB)
DDR_CH4: Start: 0x1800_0000_0000, End: 0x187F_FFFF_FFFF (512 GB)
NONE: No address region assigned to this channel slot.