NoC and Memory Controller simulation support is provided with behavioral models in either SystemVerilog (RTL in GUI) or SystemC (TLM in GUI). The simulation time with SystemC model is much faster but less accurate compared to the SystemVerilog model. While both the SystemC and SystemVerilog models can be used to verify functionality, the SystemVerilog model should be used for performance analysis. Performance includes both bandwidth and latency. Performance analysis using the SystemVerilog model shows a known variation range compared to hardware. In future releases, the range where the difference exceeds ±5% will be updated, ensuring more accurate performance predictions.
During simulation the Read Latency Estimate and Write Latency Estimate represent only the round-trip structural latency through a portion of the NoC in the AXI clock domain. These numbers do not include latency in the DRAM, memory controller, PCB routing, etc. The actual total latency is greater than these numbers. These latencies are reported in AXI clock cycles. They are intended for relative comparison between different NoC implementations, not as a representation of the actual total latency.
The SystemVerilog model is a behavioral model developed for performance analysis. The following features have minimal impact on performance and are hence not modeled for SystemVerilog nor SystemC:
- Calibration algorithm
- Memory initialization sequence – Model gets Mode Register values through parameters
- ECC - Check Bit calculation is unsupported, however performance impact due to Check Bit calculation and Read Modify Write (RMW) is modeled.
- Initializing DRAM with data patterns.
- ECC Poisoning.Note: Inline ECC adversely impacts performance. This impact has not yet been modeled.
- Scrubbing – Performance impact is insignificant because it is a background activity.
- DDR5 Command/Address Parity
- Write/Read DBI – Performance impact is modeled.
- Exclusive transactions – All transactions treated equally by the model.
- Programmable preamble and post amble for read and write.
- Self-Refresh, User Refresh.
- Page closed policy
- CA Mirror
- Sideband ECC
- LPDDR5 Per-Bank Refresh
- DDR5 Same-Bank Refresh
- Refresh Management.
- Periodic Reads
- Power Down