- DDR5 and LPDDR5/5X protocols.
- Component, RDIMM, UDIMM (CUDIMM), and SODIMM (CSODIMM) topology support.
-
Note: MRDIMM is not currently supported.
- Up to x32 data width or x40 for side-band ECC interfaces.
- Up to x16 data width for dual channel configurations.
- Supports Dual-Rank and Dual-Slot topologies.
- Quality of Service (QoS) classes:
- Read: Isochronous, Low Latency, Best Effort.
- Write: Isochronous, Best Effort.
- Out-of-order execution of commands for enhanced SDRAM efficiency.
- ECC support: Single Error Correct, Cyclic Redundancy Check
(SEC-CRC):
- 4- or 8-bit side-band ECC for DDR5.
- Inline ECC for DDR5 or LPDDR5/5X.
- On-the-fly scrubbing.
- Background scrubbing.
- Correctable and uncorrectable error logging.
- Error injection for writes.
- Side-band SEC-CRC detects all single-wire failures.
- Inline SEC-CRC detects single-wire failures with high probability.
- Command/Address Parity (DDR5 RDIMM only).
- Data Mask and Dynamic Bus Inversion (DBI).
- Fixed Burst Length 16.
- LPDDR5/5X Bank Architecture:
- BG Mode (>3200 Mbps)
- 16B Mode (≤3200 Mbps)
- 8B Mode not supported
- 1N or 2N command timing for DDR5 components and DIMM interfaces.
- Refresh support for 1x, 2x, and 4x rates for DDR5, and 1x, 2x, 4x, and 8x rates for LPDDR5/5X.
- 2x fine granularity refresh mode for DDR5.
- Same-Bank refresh for DDR5.
- Per-Bank refresh for LPDDR5/5X.
- Refresh Management.
- Read-After-Write and Write-After-Write hazard checking.
- AXI ID ordering.
- XTS-AES-256 inline encryption/decryption using a 512-bit key (two 256-bit AES keys). Metadata stored entirely on-chip; no DRAM capacity overhead. Hardware key rolling. Available on DDRMC5C and DDRMC5E only.
- AES-GCM-256 inline encryption/decryption and data integrity authentication
using a 256-bit key. Authentication metadata is stored in DRAM in one of two
modes:
- Single Level Authentication
- A 96-bit Message Authentication Code (MAC) and 32-bit Initialization Vector (IV) per 64-byte message are stored in DRAM, consuming approximately 1/4 of the GCM-protected data size. Each DRAM access requires an additional metadata transaction. Does not provide replay-attack.
- Dual Level Authentication (Second Auth)
- 1st-level MACs stored in DRAM (32-bit MAC + 32-bit IV per 64-byte message, consuming approximately 1/8 of the GCM-protected data size). 2nd-level MACs stored in on-chip SRAM (256 KB), providing replay-attack protection. GCM-protected data limited to ≤ 64 MB.
- Optional hardware DPA countermeasures. Hardware key rolling. Available on DDRMC5C and DDRMC5E only.
- Up to 16 independently configurable memory protection and encryption regions via the Extended Memory Protection Unit (XMPU). Available on DDRMC5C and DDRMC5E only.
- Inline ECC (SEC-CRC) using a (127, 120) Hamming code with parity for DDR5 and LPDDR5/5X. ECC bytes stored interleaved in DRAM. ECC storage = Protected Size / 8; max protectable capacity = (Total Memory × 8) / 9. Available on DDRMC5C, DDRMC5E, and DDRMC5X.
- 32-entry on-chip ECC Cache (ILC) to minimize DRAM read-modify-write overhead during inline ECC write operations.
- Hardware memory fill to initialize ECC check bytes after calibration completes, before user DRAM access is permitted.
- Post-implementation configuration of Inline ECC and Crypto via the AMD Advanced Configuration Editor (ACE), with final PDI generation using bootgen and an overlay CDO file.