Memory Configuration Support - Memory Configuration Support - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID: PG456
Release_Date: 2026-08-07
Version: 1.0 English

Table 1. DDR5 Component Interface
DDR Channels	Data Bus Width	Data Bus Width with Side-band ECC	DRAM Component	Max. Number of Ranks
1	32	40³	DDR5: x8, x16	1
1	16	20 or 24³	DDR5: x4, x8, x16	1
For any component interface, all memory components must be identical. Multi-rank for component interfaces is not supported. Sharing the DQ bus with multiple components as separate physical ranks on the PCB is not supported. Side-band ECC not supported with x16 components.

Table 2. DDR5 DIMM Interface
Base DDR Bus Channel Width [bits]	DIMM Type	Max. Number of Physical Ranks per DIMM	Max Number of Slots	Max Total Ranks	Data Bus Channel Width with Sideband ECC
1x32	DDR5 UDIMM/SODIMM	2	1	2	1x36
1x32	DDR5 RDIMM	2	2	4	1x40
For any DIMM interface with multiple slots, all DIMMs must be identical. UDIMM/SODIMM includes CUDIMM and CSODIMM.

Table 3. LPDDR5/5X Component Interface
LPDDR5/5X Channels	Data Bus Width	DRAM Component¹	Max. Number of Ranks¹	ECC Support
1	32	x16 channel	2	Inline
1	16	x16 channel	2	Inline
2	16	x16 channel	2	Inline
For any component interface, all memory components must be identical on a x16 channel basis. Byte-mode devices are not supported. Dual-rank for component interfaces is only supported for dual-rank packages. Sharing the DQ bus with multiple components as separate physical ranks on the PCB is not supported.