Supported configurations for LPDDR5/5X are listed under Memory Configuration Support in the DDR Memory Controller section of this Product Guide.
Recommended: You are encouraged to try the
Obtaining and Verifying Versal Adaptive SoC Memory Pinouts
tutorial available on GitHub. This is a fast and effective way to
quickly generate pinouts for Versal DDRMCs. All pin swaps
must be captured in the design's XDC and validated before generating hardware. PCB level
pin swaps not captured in the tools can lead to hardware failures if pin rules are not
followed.
Important: LPDDR5/5X protocol uses feedback
on the DQ bits during CA Training and Write Leveling calibration stages so any pin
swapping needs to be done and validated in the tools.