LPDDR5/5X Pin Rules - LPDDR5/5X Pin Rules - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English
Important: LPDDR5/5X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any pin swapping needs to be done and validated in the tools. You are encouraged to try the Obtaining and Verifying Versal Adaptive SoC Memory Pinouts tutorial available on GitHub. This is a fast and effective way to quickly generate pinouts for Versal DDRMCs. All pin swaps must be captured in the design's XDC and validated before generating hardware. PCB level pin swaps not captured in the tools can lead to hardware failures if pin rules are not followed.
  1. Command, Address, and Control pins are fixed. This includes all pins within this group:
    1. Command/Address/Control pins: CA[6:0], CS, and RESET_N.
      1. CA (Address) signals of Channel 0 can be swapped within Channel 0 and similarly CA (Address) signals of Channel 1 can be swapped within Channel 1.
      2. CA (Address) signals of Channel 0 cannot be swapped with CA (Address) signals of Channel 1.
      3. All interfaces: DMI is mapped to pin 6.
  2. RDQS/DQ/DMI Pin Guidelines that are fixed:
    1. RDQS Guidelines:
      1. x16 interfaces: RDQS_t/RDQS_c must be placed on pin 2 and 3 respectively in one of the two octads used for data nibbles.
      2. RDQS pairs must be placed in the neighboring octad of WCK (0/1, 2/3, 4/5, 6/7).
    2. DQ/DMI Guidelines:
      1. x16 interfaces: All DQ and associated RDQS/DMI must be within the octad pair (0/1, 2/3, 4/5, 6/7).
      2. All interfaces: DQs are mapped to pins 0, 1, 4, and 5 only.
      3. x16 interfaces: All DQs of word (byte pairs 0/1 & 2/3) must be placed in consecutive octads. So DQ[7:0] and DQ[15:8] pairs must be placed in consecutive octads and DQ[31:24] and DQ[23:16] pairs must be placed in consecutive octads.
  3. The following swapping is allowed for all DQ/DMI/RDQS pins:
    1. LPDDR5/5X DQ bit swap.
      Important: LPDDR5/5X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any required pin swapping must be validated in the tools.
      1. DQ bits within a byte (RDQS/DQ group) can be swapped.
        Table 1. Example of DQ Bits Swapped within a Byte
        Package pin name Un-swapped Swapped Notes
        IO_L0P_H0O0P0_M0P0_700 DQ[0] DQ[4]  
        IO_L0N_H0O0P1_M0P1_700 DQ[1] DQ[6]  
        IO_L1P_XCC_H0O0P2_M0P2_700 WCK_t[0] WCK_t[0] Cannot swap
        IO_L1N_XCC_H0O0P3_M0P3_700 WCK_c[0] WCK_c[0] Cannot swap
        IO_L2P_H0O0P4_M0P4_700 DQ[2] DQ[7]  
        IO_L2N_H0O0P5_M0P5_700 DQ[3] DQ[0]  
        IO_L3P_GC_H0O0P6_M0P6_700 DMI[0] DMI[0] Cannot swap
        IO_L3N_GC_H0O0P7_M0P7_700 CA_0[6] CA_0[6] Cannot swap
        IO_L4P_H0O1P0_M0P8_700 DQ[4] DQ[3]  
        IO_L4N_H0O1P1_M0P9_700 DQ[5] DQ[2]  
        IO_L5P_XCC_H0O1P2_M0P10_700 RDQS_t[0] RDQS_t[0] Cannot swap
        IO_L5N_XCC_H0O1P3_M0P11_700 RDQS_c[0] RDQS_c[0] Cannot swap
        IO_L6P_H0O1P4_M0P12_700 DQ[6] DQ[1]  
        IO_L6N_H0O1P5_M0P13_700 DQ[7] DQ[5]  
        IO_L7P_H0O1P6_M0P14_700 CA_0[5] CA_0[5] Cannot swap
        IO_L7N_H0O1P7_M0P15_700 CA_0[4] CA_0[4] Cannot swap
    2. LPDDR5/5X RDQS/DQ byte swap:

      When you swap byte/nibble, DQ must be swapped together with associated RDQS, WCK, and DMI. Also, RDQS, WCK, and DMI position must be intact (DQ must be swapped with DQ only, DMI must be swapped with DMI only, RDQS must be with RDQS only, and WCK must be swapped with WCK only).

      Example of byte swap:

      • Octad-0 has WCK[0], DMI[0] and DQ[3:0], Octad-1 has RDQS[0] and DQ[7:4].
      • Octad-2 has WCK[1], DMI[1] and DQ[11:8], Octad-3 has RDQS[1] and DQ[15:12].
      • When you swap the bytes, the relative position of RDQS, WCK, and DMI is fixed with respect to its original position in an octad pair.
        • When DQ[7:0] is swapped with DQ[15:8]:
          • WCK[1] must be placed in Octad-0, WCK[0] must be placed in Octad-2.
          • RDQS[1] must be placed in Octad-1, RDQS[0] must be placed in Octad-3.
          • DMI[1] must be placed in Octad-0, DMI[0] must be placed in Octad-2.
      1. Single Channel Configuration: Only swapping of byte pairs allowed. Complete swap of one x16 with another x16 allowed, swapping of one byte from one x16 with one byte from another x16 is not allowed.
        1. Example for swapping of byte pairs:
          • DQ[15:0], associated RDQS, WCK, and DM are placed in octad 0, 1, 2 and 3 of Bank x
          • DQ[31:16], associated RDQS, WCK, and DM are placed in octad 0, 1, 2, and 3 of Bank x+1
          • In this case, only a complete swap of DQ[15:0] with DQ[31:16] is allowed:
            • After swap, DQ[15:0] is placed in octad 0, 1, 2, and 3 of Bank x+1
            • After swap, DQ[31:16] is placed in octad 0, octad 1, octad 2 and octad 3 of Bank x
          • Swapping of single byte/nibble from DQ[15:0] with DQ[31:16] is not allowed:
            • Only swapping DQ[7:0] with DQ[23:16] and leaving DQ[15:8] and DQ[31:24] as is not allowed
            • Any combination of swap of only one byte from one x16 to another x16 is not allowed
        2. Example of swapping within byte pairs:
          • DQ[15:0], associated RDQS, WCK, and DM are placed in octad 0, octad 1, octad 2 and octad 3 of Bank x. Where, DQ[7:0] is placed in octad 0 and octad 1. DQ[15:8] is placed in octad 2 and octad 3.
          • DQ[31:16], associated RDQS, WCK, and DM are placed in octad 0, 1, 2, and 3 of Bank x+1. Where, DQ[23:16] is placed in octad 0 and 1. DQ[31:24] is placed in octad 2 and 3.
          • Swap with in byte pairs allowed:
            • Valid swapping example is swap of DQ[7:0] with DQ[15:8] → After swap, DQ[7:0] is placed in octad 2 and octad 3. DQ[15:8] is placed in octad 0 and octad 1
            • Another valid swapping example is swap of DQ[23:16] with DQ[31:24] → After swap, DQ[23:16] is placed in octad 2 and 3 of Bank x+1. DQ[31:24] is placed in octad 0 and 1 of Bank x+1.
      2. Dual Channel Configuration:
        1. Only swapping of bytes within a byte pair or a Channel is allowed. Swap of bytes within Channel-0 are allowed and similarly, swap of bytes within Channel-1 are allowed.
        2. Swapping of Channel-0 with Channel-1 is not allowed.
        3. Example of swapping bytes within a Channel:
          • Channel-0 DQ[15:0], associated RDQS, WCK, and DM are placed in octad 0, octad 1, octad 2 and octad 3 of Bank x. Where, Channel-0 DQ[7:0] is placed in octad 0 and octad 1. Channel-0 DQ[15:8] is placed in octad 2 and octad 3.
          • Channel-1 DQ[15:0], associated RDQS, WCK, and DM are placed in octad 0, 1, 2, and 3 of Bank x+1. Where, Channel-1 DQ[7:0] is placed in octad 0 and 1. Channel-1 DQ[15:8] is placed in octad 2 and 3.
          • Allowed swap within Channel:
            • Channel-0 DQ[7:0] swap with Channel-0 DQ[15:8] → After swap, Channel-0 DQ[7:0] is placed in octad 2 and octad 3 of Bank x. Channel-0 DQ[15:8] is placed in octad 0 and octad 1 in Bank x.
            • Channel-1 DQ[7:0] swap with Channel-1 DQ[15:8] → After swap, Channel-1 DQ[7:0] is placed in octad 2 and 3 of Bank x+1. Channel-1 DQ[15:8] is placed in octad 0 and 1 of Bank x+1.
          • Channel-0 DQ[15:0] must not be swapped with Channel-1 DQ[15:0]
  4. DQ, and associated RDQS/RDS, WCK and DM must be in consecutive octad pairs: 0/1, 2/3, 4/5, 6/7 of Bank. For example, DQ[7:0], RDQS[0], WCK[0], DM0 must be placed in consecutive octad pairs. Similarly, DQ[15:8], RDQS[1], WCK[1], DM0 must be placed in consecutive octad pairs.
  5. In X5PHIO bank 700 and bank 800 (not present in all devices), there is an additional bank pin that is used as a reference to calibrate internal on-die termination. The IO_VR_700/ IO_VR_800 pin must be externally connected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage.
  6. One differential system clock source (sys_clk) is required per integrated DDRMC5. For example, in a design with two adjacent MCs, the sys_clk can be placed in the adjacent bank. In a design with two interfaces occupying Bank 700, 701, 702, 703, 704, and 705, both sys_clk pairs can be placed on the clock capable pins of bank 702 or 703. The sys_clk pair must be placed on an available clock capable pin pair within the three Banks associated with a DDRMC5. Refer to Clocking for details.
  7. For a single MC interface the sys_clk can be placed in any of the banks where the interface is located.
    Example
    In a design with an interface occupying Bank 700, 701, or 702, the sys_clk can be placed in any of the three banks. Similarly for an interface in the next three consecutive banks (703, 704, 705) the sys_clk can be placed in any of the three banks.
    Example
    In a design with an interface occupying Bank 700 and 701, the sys_clk can be placed in Bank 700, 701, or 702. Similarly, for an interface occupying Bank 703 and 704 the sys_clk can be placed in 703, 704, or 705.
    Note: Allowed combinations for six consecutive banks are Banks: '700, 701, 702, 703, 704, 705' and Banks '706, 707, 708, 709, 710, 711'
  8. In a design with two interfaces occupying six consecutive banks and no sys_clk sharing, the sys_clk can be placed in the respective banks of each interface. The sys_clk can also be placed in the adjacent bank of the other interface.
    Note: This rule only applies to above mentioned six consecutive bank configuration.
    Example
    In a design with an interface occupying Bank 706, 707, and 708 and the second interface occupying Bank 709, 710 and 711:
    • sys_clk of the first interface can be placed in Bank 706, 707, or 708
    • sys_clk of the second interface can be placed in Bank 709, 710, or 711
    • sys_clk of the first interface can be placed in Bank 709 and sys_clk of second interface can be placed in Bank 708
  9. In a design with two interfaces occupying six consecutive banks with sys_clk sharing, the sys_clk must be placed in the middle two banks of the six bank interface.
    Note: sys_clk sharing is only allowed in the above mentioned six consecutive bank configuration.
    Example
    In a design with an interface occupying Banks 706, 707, and 708 and the second interface occupying Banks 709, 710, and 711:
    • With sys_clk sharing, the sys_clk can be placed in either Bank 708 or 709.
  10. The reset_n signal is fixed and cannot be moved.
  11. Unused pins in an octad can be utilized for non-memory designs for route through only.