| DDRMC5X: no Crypto block |
Inline encryption is not available on DDRMC5X. Inline ECC is
available on all three variants without restriction. |
| CA Parity Retry incompatible |
Disabled when inline ECC or Crypto is enabled. No DDRMC5 variant
supports DDR5 RCD CA Parity Retry with either feature active. CA
Parity error detection remains functional; only retry is disabled,
making CA Parity errors fatal in these configurations. |
| XTS: no AXI exclusive access |
Exclusive AXI transactions to XTS-AES-256 encrypted regions are
not supported on DDRMC5 or DDRMC5C. Exclusive access to AES-GCM or
unencrypted regions is supported normally. |
| GCM: WAR hazard checking |
AES-GCM requires Write-After-Read (WAR) address hazard checking
in the DRAM Controller Transaction Queue (TXNQ) in addition to
standard RAW and WAW checking. Automatically configured when GCM is
enabled. |
| GCM: DRAM bandwidth overhead |
GCM reduces throughput to 2 GB/s. Use XTS-AES-256 for large regions
where this is unacceptable. |
| No dynamic region resize |
Encrypted region sizes and key allocations are fixed at boot
time. A full Power-On Reset is required to change them. |
| Interleave constraint |
For encrypted interleaved designs: interleave granularity must
satisfy interleave size ≤ (region size/number of interleave
ways). |