|
Core Specifics |
| Supported Device Family
1, 3
|
AMD Versal™ AI Edge Series Gen
2,
Versal Prime Series Gen 2, Versal Prime VM2152 device, Versal Premium Series Gen 2, Versal RF Series |
| Supported User Interfaces |
AXI3, AXI4, AXI4-Stream
|
| Provided with Core |
| Test Bench |
Verilog |
| Constraints File |
XDC |
| Simulation Model |
SystemVerilog, SystemC |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™
IP
Integrator |
| Simulation |
Questa Advanced Simulator,
Cadence Xcelium Parallel Simulator, Synopsys VCS, Vivado
Simulator. |
| Synthesis |
AMD Vivado™
Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 75764
|
| All Vivado IP
Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- For other Versal
device support, refer to the
Versal Adaptive SoC Programmable Network on Chip and
Integrated Memory Controller LogiCORE IP Product Guide (PG313).
|