The Versal adaptive SoC uses the PMC I2C Master exclusively to communicate with all DDR5 RDIMM and CUDIMM/CSODIMM devices. All instances of RDIMM and CUDIMM/CSODIMM devices in a design must share a single PMC I2C Master bus — there is no support for using the PS I2C or any other I2C master for DIMM initialization.
Important: Do not use the PS I2C or PL I2C master for DIMM
initialization. Only the PMC I2C Master can perform the required DIMM initialization
sequence. Do not insert any multiplexors in the I2C path between the Versal PMC and the DIMM because the PMC cannot control them during boot.
Note: I3C is permitted by JEDEC standards. To ensure I3C
compatibility on the DIMM side, operate HSCL and HSDA at 1.0V. However, the current Versal IP implementation uses I2C mode only (maximum 1
MHz). If HSCL/HSDA operate at 1.8V, only I2C mode is possible on the DIMM side. Refer to
HSCL and HSDA—Voltage and Pull-up Requirements for voltage and pull-up resistor
requirements.