Host Sideband Signals (HSA, HSCL, HSDA) - Host Sideband Signals (HSA, HSCL, HSDA) - 1.0 English

Host Sideband Signals (HSA, HSCL, HSDA) - Host Sideband Signals (HSA, HSCL, HSDA) - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID

PG456

Release_Date

2026-08-07

Version

1.0 English

For all RDIMM and CUDIMM/CSODIMM designs, three host sideband signals must be connected directly from the Versal PMC I2C interface to each DIMM slot:

Table 1. Host Sideband Signal Summary
Signal	Full Name	Function	PCB Connection Requirement
HSA	Host SidebandBus Address	Sets the 3-bit HID for all devices on this DIMM slot	Pull-down resistor to GND — value determines HID. Refer to the following table.
HSCL	Host SidebandBus Clock	I2C/I3C clock from PMC to DIMM HUB device	Direct from PMC MIO. Level shifter may be required. 2.2 kΩ pull-up at DIMM side if using level shifter.
HSDA	Host SidebandBus Data	I2C/I3C bidirectional data between PMC and DIMM HUB device	Direct from PMC MIO. Level shifter may be required. 2.2 kΩ pull-up at DIMM side if using level shifter.