Error Correction (Single Error Correct, Cyclic Redundancy Check) performs checks of read data without interrupting traffic. The DDRMC5 supports both side-band ECC as well as inline ECC. Both modes are supported with DDR5, but the modes are mutually exclusive. LPDDR5/5X only supports inline ECC. The side-band ECC calculations are stored in an additional nibble or byte. Side-band ECC supports x40, x36, x24, and x20 total bus widths. Inline stores ECC bits in separate memory locations than data, and it has a standard bus width of x32 or x16.
For each burst, single-bit errors are correctable. Double-bit errors are detectable but uncorrectable. Multi-bit errors are detected with high probability, but are not correctable. If any errors are detected, correctable or uncorrectable, they are logged and can be configured to generate an interrupt. Correctable and uncorrectable errors can be injected on write operations.