A new behavior for the DDRMC5 is that the memory simulation responder model exists at the top level of the design and can be seen on the IP integrator canvas. The following figure shows an example with one DDRMC5 instance set to LPDDR5 Dual Channel x16 mode and another DDRMC5 set to LPDDR5 Single Channel x32 mode.
Not all Automation or Designer Assistance flows automatically add and connect the DDRMC5 Responder Core in a Block Design; sometimes it needs to be added manually. This can be done by right-clicking on the IP integrator canvas, selecting Add IP…, and then searching for DDRMC. The DDRMC5 Responder Core appears in the results.
When the DDRMC5 Responder Core is added to the IP integrator canvas, it might be necessary to change some settings to make the interface connections. The following figure shows an example of the exposed Dual Channel 2x16 LPDDR5 interface ports on a NoC2 instance. The default configuration for the DDRMC5 Responder Core does not match this use case and must be reconfigured.
Double-click the DDRMC5 Responder Core IP to open the Configuration GUI.
To match the DDRMC5 settings the Memory Responder
Type needs to be set to LPDDR5 SDRAM and the
Number of Channels needs to be set to
Dual.
With the updated DDRMC5 Responder Core settings the DDRMC5 instance can be connected to the simulation model. To finalize the process, make the responder model ports external in the Block Design.