All references to register names in the following sections can be obtained from the Vivado Hardware Manager Properties window and Properties tab, or via the Tcl command described in the previous section.
The register names provided in this section can be matched to register names in the Versal Adaptive SoC AIE-ML v2 Register Reference (AM029) and the Versal AI Edge Series Gen 2 and Prime Series Gen 2 NoC and Integrated Memory Controller NPI Register Reference (AM033). This document provides the NPI address values for each register, enabling you to implement your own method to check the calibration status. In this document, there are two sections: DDRMC5_DDR5_XRAM Module and DDRMC5_LPDDR5_XRAM Module. Select the appropriate module based on the target memory interface type, as the register contents and locations vary.
| Register Name | Description (in Decimal) |
|---|---|
| MEM_TYPE | 1: Integrated Memory Controller DDR5 2: Integrated Memory Controller LPDDR5/5X |
| PHY_RANKS | Number of XPHY Ranks |
| MEM_RANKS | Number of Memory Ranks |
| BYTES | Number of Bytes in the Memory Interface |
| NIBBLES | Number of Nibbles in the Memory Interface |
| BITS_PER_BYTE | Bits per byte (4 or 8) |
| SLOTS | Number of Slots in the Memory Interface |
| DIMM_TYPE |
|
| LRANKS | Number of Logical Ranks |
| NUM_CHANNELS | Number of Memory Channels |
| DRAM_SIZE | Size of the DRAM components |
| SYS_CLK_8_0 | System clock period (in ps): LSB |
| SYS_CLK_17_9 | System clock period (in ps): MSB |
| ECC_EN | Bit 0 - Inline, Bit 1 - Side band, Bit 2 - On-die |
| MISSION MODE SETTINGS |
|