DDR5 x8/x16 Component (x16 to x40 Data Width) - DDR5 x8/x16 Component (x16 to x40 Data Width) - 1.0 English - PG456

DDR5 x8 and x16 components support data widths from x16 up to x40 (with sideband ECC). Each x8 component maps to two consecutive octads (an octad pair — one byte). DQS_t/c occupies pins 2 and 3 of one octad in the pair; DM occupies pin 6 of the adjacent octad. CA bits are distributed in the GC-capable pin positions (pins 6/7) across the data octads; CK_t/c and remaining control signals occupy the pin positions in later data octads.

The x40 configuration (5 × x8 components = 10 data octads) is shown as the representative — it uses all three banks. Narrower widths leave progressively more octads in Bank x+2 as FREE.

x32 (4 bytes = 8 octads): Bank x+2 Octads 2 and 3 FREE.

Figure 1. Octad Utilization for DDR5 x8/x16 Component — x40 Data Width