DDR5 (x8) Pinout for 80-bit 2 Rank RDIMM Interfaces - DDR5 (x8) Pinout for 80-bit 2 Rank RDIMM Interfaces - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

Octad utilization for 80-bit, 2 Rank RDIMM with ECC is shown in the following figure. DQ is the bi-directional data bit, DQS_t/c is the differential data strobe, DM_n is data mask, CK_t/c is the differential clock pair, CA indicates Command/Address bits, CS is Chip Select, reset_n is the reset input to the RDIMM, ALERT_N is a bi-directional signal to/from the RDIMM, PAR is the parity input to the RDIMM, LBDQ-S is the loopback data output from RDIMM, and SYS_CLK indicates the System Clock pair.

Important: The octad utilization figure is based on the pinout output by Vivado for this configuration.
Figure 1. Octad Utilization for 80-bit 2 Rank RDIMM with ECC