DDR5 x4 components support x16 (four components) and x20 (five components, with
4-bit sideband ECC) data widths. Each x4 component maps to one octad. DQS_t/c is placed in the same octad as DQ (pins 2 and 3). DM is
at pin 6 of each data octad. CA[5:0] bits are
distributed across the GC-capable pins (6/7) of the data octads; CA[13:6] and the CK_t/c
clock pair occupy a dedicated control octad.
For x16, data occupies all four octads of Bank x; Bank x+2 is entirely free. For x20, the fifth ECC nibble is placed in Bank x+1 Octad 1 (shown as FREE with the x20 note below).
Figure 1. Octad Utilization for DDR5 x4 Component — x16 Data Width
