Figure 1. Configure DDRMC5 — DDR Advanced Tab (DDR5 DIMM)
DDR5 2T (2N Mode)
Enables 2T (also referred to as 2N) command timing, which drives command/address signals for two clock cycles instead of one.
- DISABLE
- Standard 1T (1N) command timing.
- ENABLE
- 2T (2N) command timing for improved signal integrity.
RDIMM Address Mode
Selects the command address mode for the DDR5 registered clock driver (RCD). This option controls whether the RDIMM register uses DDR or SDR signaling for the command and address bus.
- DDR (default)
- Double Data Rate command/address signaling.
- SDR
- Single Data Rate command/address signaling. Provides more timing margin at the cost of reduced command bandwidth.
Refresh Options
- Refresh Type
- Selects the refresh scope applied by the controller during the refresh
interval.
- ALL_BANK (default)
- All-bank refresh activates all banks simultaneously for maximum refresh efficiency.
- SAME_BANK
- Same-bank refresh. When selected, Refresh Mode is automatically set to FINE_GRANULARITY and grayed out.
- Refresh Mode
- Selects the refresh mode for the DDR5 controller.
- NORMAL (default)
- Standard refresh mode using conventional all-bank or same-bank refresh commands.
- FINE_GRANULARITY
- Fine-granularity refresh (FGR) mode, which distributes refresh operations more evenly over time by doubling the refresh frequency and halving the number of rows refreshed per command. Automatically enabled and grayed out when Refresh Type is set to SAME_BANK.
- Enable User Refresh
- When selected, disables automatic controller-managed refresh and requires the host to issue refresh commands via the refresh interface.
- Self Refresh
- Selects the self-refresh entry strategy.
- DISABLE (default)
- Self-refresh is not used.
- ACTIVITY_BASED_SR
- Controller enters self-refresh automatically during periods of inactivity.
- Clock Stopped Self Refresh
- When selected, enables clock-stopped self-refresh mode. The memory clock stops during self-refresh to further reduce power consumption. The DRAM device maintains data using its internal refresh oscillator while the external clock is gated.