DDR5 component interfaces support two pinout options: Packed to the Left (default) and Packed to the Right. The signal grouping and number of octads used differs between x4 and x8/x16 component widths because they support different maximum data widths.
| Property | DDR5 x4 Component | DDR5 x8/x16 Component |
|---|---|---|
| Supported data widths | x16, x20 (with sideband ECC) | x16, x24, x32, x40 |
| Octads used for data | 4 (x16) or 5 (x20) | 4 (x16) up to 10 (x40) |
| DQS placement rule | DQS_t/c in the SAME octad as DQ (1 octad per x4 nibble) | DQS_t/c in ONE octad of the 2-octad byte pair (x8/x16 octad pair rule) |
Important: The octad utilization figures are
representative signal groupings. Always use Vivado tools to obtain
the authoritative pinout for your specific device, package, and data width
configuration.