Configuring Inline ECC (per ILECC controller) - Configuring Inline ECC (per ILECC controller) - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English
  1. In the left panel, click /axi_noc2_N/ddrmc for the target controller (replace 'N' with the instance number).
  2. Check the Inline ECC check box. ACE automatically calculates and displays the ECC memory partitioning (Max ECC Protected Size, ECC Storage Size, Non-Protected Size, Available Memory). Refer to the Inline ECC Memory Partitioning table for formulas.
  3. Optionally, set ECC Offset if the ECC-protected region does not start at the DDR controller base address.
  4. Enable adec_chk_enable_log to generate an interrupt on accesses outside the available ECC-protected region. The error count in Settings & Messages decreases by one for each successfully configured controller.