Clocking - Clocking - 1.0 English - PG456

When an axi_noc2 instance is configured to include an external DDR5 or LPDDR5/5X memory interface, one sys_clk port appears on the boundary of the IP. When multiple controllers are interleaved within a single axi_noc2 instance, each DDRMC5 exposes a sys_clk port. When interleaving DDRMC5s the sys_clk configuration is identical across all controllers. The sys_clk is used internally by the DDRMC5 to generate the various clocks for the controller and external memory interface. The DDRMC5 has three options for the System Clock. These are Differential, No Buffer, and Internal. The System Clock options are in the DDR Basic tab of the DDRMC5 configuration GUI.

Differential

The DDRMC5 sys_clk port must be connected to an AC-coupled DC-biased differential clock source matching the user-selectable frequency in the DDR Basic tab of the DDRMC5 Configuration GUI. The differential clock source must be placed on the Global Clock (GC) pair determined by the DDRMC5 pin and bank rules as well as the bank location. See Memory Controller Pinout Rules for more details. The IP automatically generates IO Standard constraints for the DDRMC5 sys_clk. These constraints cannot be changed as they are the expected settings to work with the reference AC-coupled and DC-biased circuit. The following figure shows the system clock circuit driven by an LVDS source. VCCO is determined by the selection of either DDR5 (1.1V) or LPDDR5/5X (1.0V).

Figure 2. Universal AC-Coupled DC-Biased Differential DDRMC5 System Clock Circuit

No Buffer

The No Buffer option can be used when two adjacent DDRMCs share a common Bank between their three banks. Both DDRMC5 instances need to have the same memory interface type (DDR5 or LPDDR5/5x) and running at the same data rate. To share a single clock source for both DDRMC5 instances, set the System Clock option to No Buffer. On the IPI canvas, add a Utility Buffer with a single differential input and two outputs. Then route one output to each single-ended sys_clk pin. The external differential input clock for the No Buffer option has the same circuit topology and constraint expectations as the dedicated Differential system clock described above. See Memory Controller Pinout Rules for more details on pin and bank expectations. The following figure shows an example of this topology with the Utility Buffer IP. The Versal AI Edge Series Gen 2 VEK385 Evaluation Kit uses the No Buffer option for the LPDDR5 in Banks 700-704.

Figure 3. AXI NoC2 sys_clk inputs Driven from Utility Buffer IP

Internal

The Internal option allows for the internally generated HSM1 clock from the PMC to be routed to any DDRMC5 instance in the design. All DDRMC5 instances using the HSM1 clock all need to be configured for the same System Clock frequency. The supported operating range for the HSM1 clock is 100 MHz to 200 MHz. When the Internal option is enabled, single-ended sys_clk ports are exposed at the top level of the NoC2 instance. The CIPS or PSWizard needs to be included in the Block Design to use the HSM1 clock. Open the CIPS/PSWizard configuration GUI and go to the Clocking section and then the Output Clocks tab. Expand the PMC Domain Clocks and then the Processor/Memory Clocks to see the HSM1 clock options.

Figure 4. HSM1 Clocking Options

The HSM1 clock port needs to be exposed on the IPI canvas and then connected to the DDRMC5 sys_clk ports. In the CIPS/PSWizard configuration GUI, go to the PS NoC Interfaces section. At the bottom of the section, enable the PS to NoC Clocks check box to expose the HSM1 Clock Port.

Figure 5. Enable DDRMC HSM1 Clock Port

Now connect the HSM1 clock to the DDRMC5 instances.

Figure 6. HSM1 Clock to DDRMC5 Connections