Memory Clock Period (ps)
Specifies the target memory interface clock period in picoseconds. Shorter periods correspond to higher data rates.
- For LPDDR5 SDRAM: Valid range is 938–12500 ps:
- 938 ps
- Maximum data rate: LPDDR5X-8533 (8533 Mbps).
- 12500 ps
- Minimum data rate: approximately 640 Mbps.
- For DDR5 SDRAM: Valid range is 313–625 ps:
- 313 ps
- Maximum data rate: DDR5-6400 (6400 MT/s).
- 625 ps
- Minimum data rate: DDR5-3200 (3200 MT/s).
Note: The default value reflects the minimum clock period for the
highest supported speed grade. The selected Speed Bin (configured in the
DDR Memory Options tab) determines the
minimum valid clock period.
Input System Clock Period (ps)
Selects the period of the system-level reference clock supplied to the DDRMC5, displayed with its equivalent frequency. The available values depend on the controller type and speed grade.
System Clock
Selects the physical clock topology for the reference clock input.
- Differential
- Standard differential LVDS reference clock
(
sys_clk_p/n). - No_Buffer
- Single-ended reference clock without a buffer
(
sys_clk_i). - Internal
- Reference clock sourced from the High-Speed Master (HSM1) reference clock configured in the Processing System (PS) block. Select this option when using the PS HSM1 clock output to drive the DDRMC5 reference clock.