Calibration Error Codes - Calibration Error Codes - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English
Code Error
1 XPLL Timeout Waiting for lock
2 TX FIFO Sync not complete
19 XPHY BISC calibration not complete
20 XPHY BISC timeout
21 XPHY BISC found dly qtr value to be 0
22 External write leveling stable 0 to noise region detection using coarse taps failed
23 External write leveling stable 0 to noise region detection using fine increments of step size 8 failed
24 External write leveling stable 0 to noise region detection using fine increments of step size 1 failed
25 External write leveling stable 1 window detection using fine increments of step size 1 failed
26 Internal write leveling noise detection using internal mem delay failed
27 Internal write leveling stable 0 region detection using coarse taps failed
28 Internal write leveling stable 0 to noise region detection using coarse taps failed
29 Internal write leveling stable 0 to noise region detection using fine taps failed
30 Internal write leveling stable 0 to noise region detection using fine taps of step size 1 failed
31 Internal write leveling stable 1 valid window detection using fine taps of step size 1 failed
32 DQS Gate calibration not done
33 DQS Gate calibration failed
34 DQS Gate failed to find first edge of DQS using coarse taps
35 DQS Gate failed to find noise width of DQS using fine taps
36 DDR5 can send DQS early and even with early DQS cannot get skew data
49 Read DQ PQTR incorrect (Left window > Right window)
50 Read DQ insufficient PQTR window
51 Read DQ incorrect NQTR
52 Read DQ insufficient NQTR window
53 Read DQ sanity check failed
64 Read DBI incorrect PQTR setting
65 Read DBI insufficient PQTR window
66 Read DBI incorrect NQTR setting
67 Read DBI insufficient NQTR window
68 Read DBI sanity check
69 Write DQ-DBI noise to valid region detection using fine increments failed
73 Write DQ-DBI final sanity check failed
74 Write DQ-DBI final sanity check failed after common delay adjustment failed
75 Write complex noise to valid region detection using fine increments failed
79 Write complex final sanity check failed
85 Write DQS-DQ/DM noise to valid region detection using fine increments failed
89 Write DQS-DQ/DM final sanity check failed
90 Write DQS-DQ/DM complex noise to valid region detection using fine increments failed
94 Write DQS-DQ/DM complex final sanity check failed
100 Read sanity check failed
101 Write sanity check failed
102 Memory retention sanity check failed
103 LFSR sanity check failed
104 Back to Back R/W only for DDR5
105 Complex pattern sanity check failed
106 PRBS pattern sanity check failed
107 Duty cycle adjustment of WCK this error occurs when TAP value overflows and there is not enough margin
124 Mission mode refresh management configuration failed
125 Mission mode frequency switch failed
126 Mission mode during crypto memory fill, MicroBlaze found zeroise error
127 Mission mode crypto known answer test failed
129 High temperature failure
131 After refresh management if clock was powered down DQS Gate cal is run again and it failed
133 CH0 Scrub FSM in MC timed out
134 CH1 Scrub FSM in MC timed out
135 Computed DQS path delay is out of range
136 DQS Tracking DQ delay out of range
137 DQS Tracking DM delay out of range
142 Failed to disable mission mode during 2D eye scan entry
143 Write margin check failed
144 Read margin check failed
145 Failed to enable mission mode during 2D eye scan exit
146 Margin check failed
147 Post calibration error
154 Read DQ Complex incorrect PQTR setting
155 Read DQ Complex insufficient PQTR window
156 Read DQ Complex incorrect NQTR setting
157 Read DQ Complex insufficient NQTR window
158 Read DQ Complex sanity check failed
174 RD DQ complex incorrect PQTR (L>R)
175 Read DBI Complex insufficient PQTR window
176 RD DQ complex incorrect NQTR (L>R)
177 Read DBI Complex insufficient NQTR window
178 Read DBI Complex sanity check failed
188 Write VREF training optimal setting not found
189 Write VREF training sanity check of setting failed
190 Write VREF training mismatch
191 Read VREF training optimal setting not found
192 Read VREF training sanity check of setting failed
193 Read VREF training vref mismatch
194 FSM in PHY failed to find UI equivalent of fine tap
195 FSM in PHY stuck while finding UI equivalent of fine tap
196 CA & CS calibration failed to exit
197 CA & CS calibration unknown code
198 CA & CS vref center failed
199 (DDR5 RDIMM) Register write to RW00 failed
200 (DDR5 RDIMM) Register write to RW05 failed
201 (DDR5 RDIMM) Register write to RW056 failed
202 (DDR5 RDIMM) Register read from RW00 failed
203 (DDR5 RDIMM) Register read from RW04 failed
204 WL Delay overflow
205 RL Delay overflow
206 QTR Delay overflow
220 Sanity check of P_N offset failed to find left margin with simple pattern
221 Sanity check of P_N offset failed to find right margin with simple pattern
222 Sanity check of PDQS left margin failed with simple pattern
223 Sanity check of PDQS right margin failed with simple pattern
224 Sanity check of NDQS left margin failed with simple pattern
225 Sanity check of NDQS right margin failed with simple pattern
226 Sanity check of DQ WL delay left margin failed with simple pattern
227 Sanity check of DQ WL delay right margin failed with simple pattern
230 Sanity check of P_N offset failed to find left margin with simple pattern
231 Sanity check of P_N offset failed to find right margin with simple pattern
232 Sanity check of PDQS left margin failed with complex pattern
233 Sanity check of PDQS right margin failed with complex pattern
234 Sanity check of NDQS left margin failed with complex pattern
235 Sanity check of NDQS right margin failed with complex pattern
236 Sanity check of DQ WL delay left margin failed with complex pattern
237 Sanity check of DQ WL delay right margin failed with complex pattern
240 Sanity check of P_N offset failed to find left margin with PRBS pattern
241 Sanity check of P_N offset failed to find right margin with PRBS pattern
242 Sanity check of PDQS left margin failed with PRBS pattern
243 Sanity check of PDQS right margin failed with PRBS pattern
244 Sanity check of NDQS left margin failed with PRBS pattern
245 Sanity check of NDQS right margin failed with PRBS pattern
246 Sanity check of DQ WL delay left margin failed with PRBS pattern
247 Sanity check of DQ WL delay right margin failed with PRBS pattern