CUDIMM/CSODIMM modules incorporate an integrated clock buffer that requires initialization through I2C for high data rates. There is no separate CUDIMM/CSODIMM selection in the DDRMC5 GUI — the IP uses the UDIMM/CSODIMM selection and determines the appropriate initialization behavior automatically based on the configured memory clock period:
- Clock buffer initialization required
- Memory clock period ≤ 313 ps (data rate ≥ 6.4 GT/s): The clock buffer on the CUDIMM/CSODIMM requires initialization through I2C. The PMC I2C Master must be connected and properly configured. The IP automatically initializes the clock buffer during the calibration sequence.
- Clock buffer in bypass mode (no I2C required)
- Memory clock period > 313 ps (data rate < 6.4 GT/s): The clock buffer operates in default bypass mode. I2C initialization of the clock buffer is not required and the PMC I2C connection is not used for this purpose. The CUDIMM/CSODIMM operates identically to a standard UDIMM/SODIMM at these data rates.
Note: For CUDIMM/CSODIMM at data rates < 6.4 GT/s, the
clock buffer bypass mode is the default and no explicit I2C configuration is required.
However, PMIC initialization through I2C is still required if the DIMM PMIC needs to be
powered on by I2C for all CUDIMM/CSODIMM data rates.