CS Calibration
In this stage of calibration CS is center aligned with CK. The memory device/RCD is kept in CS or Command Bus Training mode, address and CS pattern are sampled by the memory/RCD device, and the sampling status is provided on the DQ lines. Based on the sampling status the CS lines are delayed and center aligned.
CA Calibration
In this stage of calibration CA is center aligned with CK. The memory device/RCD is kept in CA or Command Bus Training mode, address and CS pattern are sampled by the memory/RCD device, and the sampling status is provided on the DQ lines. Based on the sampling status the CA lines are delayed and center aligned. To perform the CA calibration the memory device is kept in CA training mode. The CA bits are XORed, sampled on the rising edge of the CK on the CS assertion, and the sampling status is provided on DQ lines. This calibration stage uses odelays of the CA lines, CA bit slips, and tx 90 phase shift of the CA lines.