DDR5 and LPDDR5/5X DRAM both support auto-precharge functionality, whereby the activated bank is automatically precharged at the earliest possible moment during the burst read, write or masked write command. This feature enables the precharge operation to be partially or completely hidden during burst read cycles (dependent upon read or write latency), thus improving system performance for random data access. DDRMC5 can be configured to enable or disable auto-precharge operations. When enabled, the controller automatically enables auto-precharge on a CAS command when the CAS is the last page hit in the controller for a given bank. This can make a big difference in DRAM efficiency, depending on the traffic workload. For example, 64-byte random traffic efficiency benefits when auto-precharge is enabled.