The Memory Controller supports DDR5 RDIMM RCD Address and Command Parity. If a
parity error is detected by the RCD, ALERT_n is driven
low and detected by the memory controller. The controller halts all traffic and attempts
a retry of the failed command. This requires significant effort by the controller and
physical interface (PHY) to recover and retry. The PHY buffers need to be flushed, which
might have a latency impact of several microseconds. As a result, isochronous latency is
not guaranteed, and bandwidth requirements might not be met in this scenario. If an
ALERT_n is detected during the retry attempt, the
memory controller issues a fatal interrupt. The DDRMC5 cannot recover from an ALERT_n event during retry. A system reboot is needed and
memory contents is lost.
All ALERT_n assertions are fatal when inline ECC
is enabled.