The 2x16 dual-channel configuration supports three pinout options for
both single rank and dual rank. The following figures show a single set of diagrams
covering both rank configurations. One of the differences between single rank and
dual rank is the number of Chip Select signals — dual rank uses CS[1:0] per channel, single rank uses only CS[0].
CS[1:0]
with CS[0].Optimum
The interface is justified across all three half-banks with CA/Control signals in the center half-bank (HB1/Bank x+1). Channel B data occupies HB0/Bank x; Channel A data and SYS_CLK occupy HB0/Bank x+2.
Packed to the Left
The interface is justified and packed starting from HB0/Bank x. Channel A data occupies Bank x with CA[6:1] distributed across the data octads. Channel B data occupies HB1/Bank x+1. SYS_CLK and dual-rank CS signals occupy the Most Significant Octad of HB0/Bank x+2. Two upper octads of HB0/Bank x+2 remain free.
Packed to the Right
The interface is justified and packed starting from HB0/Bank x+2. Channel A data occupies Bank x+2 with CA[6:3] distributed in the data octads. Channel B data occupies HB1/Bank x+1. CA[6:0] and CS/CK occupy octads 2 and 3 of HB0/Bank x. Two lower octads of HB0/Bank x remain free.