1x32 (Single Channel, 1 CA) — Options: Packed Left, Packed Right, Packed Right with Optimum - 1x32 (Single Channel, 1 CA) — Options: Packed Left, Packed Right, Packed Right with Optimum - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

The 1x32 single-channel configuration supports three pinout options. Packed to the Left, single rank, and dual rank figures are shown separately because Bank x+2 Octad 0 differs structurally: single rank places only SYS_CLK there, while dual rank also places CS[3:2]. For Packed to the Right and Packed to the Right with Optimum, a single combined figure is shown; the only difference between ranks is the CS signal count, noted inline with *.

Packed to the Left

Starts at HB0/Bank x with DQ[15:0] data and CA[6:1] distributed across the four data octads. HB1/Bank x+1 carries DQ[31:16] data along with CK, CA[0], CS, DMI, and reset_n. SYS_CLK (and CS[3:2] for dual rank) is placed in Octad 0 of HB0/Bank x+2. Remaining octads of HB0/Bank x+2 are free.

Figure 1. Octad Utilization for 1x32, 1 CA, Packed to the Left

Packed to the Right

Starts at the Most Significant Octad of HB0/Bank x+2, which carries DQ[15:0] data with CA[6:3] distributed in the data octads and SYS_CLK in Octad 0. HB1/Bank x+1 carries DQ[31:16] with CK, CA[0], CS, DMI, and reset_n. Octad 3 of HB0/Bank x holds CA[2:1] (and CS[3:2] for dual rank); remaining octads of Bank x are free.

Note: CS[3:2]* in HB0/Bank x Octad 3 is dual rank only. For single rank, Octad 3 contains CA[2:1] only.
Figure 2. Octad Utilization for 1x32, 1 CA, Packed to the Right — Single and Dual Rank

Packed to the Right with Optimum Pinout

A variant of Packed to the Right for packages with restricted bank pin counts (for example the T20 5-2-5 package). The key difference from standard Packed to the Right is the placement of CA[2:1]:

Packed to the Right
Packed to the Right places CA[2:1] at Octad 3 of Bank x (pins 6–7). In restricted packages these pin positions do not exist.
Packed to the Right with Optimum
Packed to the Right with Optimum moves CA[2:1] into Bank x+2 Octad 0 (alongside DQ[15:12] and RDQS[1]) and places only SYS_CLK_p/n (2 pins) in Octad 0 of Bank x. When the Internal System Clock is used, Bank x is entirely free and the interface fits within two banks.
Note: CS[1:0]* in HB1/Bank x+1 Octad 0 reflects dual rank. For single rank, replace CS[1:0] with CS[0].
Figure 3. Packed to the Right Generated by Your Tool
Figure 4. Packed to Right with Optimum Option for LPDDR5/5X 1x32 — Single and Dual Rank
Note: Only the SYS_CLK_p/n pair (pins 0–1 of Octad 0) is placed in HB0/Bank x. When you select the Internal System Clock option, HB0/Bank x is entirely free and the interface uses only two banks (HB1/Bank x+1 and HB0/Bank x+2).