Each of the SI and MI on the AXI Switch core can be configured with a data width of 32, 64, 128, 256, 512, or 1024 bits (for AXI4 or AXI3 interfaces). When a transaction at an SI targets an MI with a different data width, width conversion is automatically performed along the pathway.
The width conversion transformations differ depending on whether the data-path width widens (upsizing) or narrows (downsizing) when moving from the SI toward the MI.