The transaction ID signals that propagate internally from SI to MI (awid and arid) and back again
(bid and rid), control both the routing of response
transfers, and the ordering of AXI response transfer propagation within the AXI Switch.
Endpoint master devices can optionally output awid and
arid signals that the master device can use to select among multiple
threads of transactions (as though the master device was comprised of multiple masters
internally). The reordering depth is the total number of ID values that can be generated by a
master, up to a maximum determined by the width of the master’s ID signals. Master devices
with a reordering depth of one do not need ID signals on their interface. The width of ID
signals might vary among SI.
AXI transaction ordering rules are as follows:
- There are no rules regarding the relative ordering between write transactions and read transactions.
- Transactions (of each direction) belonging to the same thread (ID value) must be returned in order.
- Transactions (of each direction) among different threads can be returned out-of-order.
All response transfers on R or B channels of a SI contain rid or bid values that match the
arid or awid (if present)
of the original commands issued by the master on the AW or AR channel of the SI.
When an SI is configured in single-ordered mode (number of ID threads = 1), all IDs received on the SI are stored and retrieved locally at the SI. The only information propagated and stored internally at the targeted MI is the identity of the originating SI for purposes of routing response transfers. The connected master might still issue multiple outstanding transactions, and the transaction IDs (if any) might have any value. However, all transactions received at the SI are propagated and returned in order. This results in the most resource-efficient when the core is configured with STRATEGY==BALANCED or AREA, all SI are configured as single-ordered.
If an SI is configured as multi-threaded (supporting a number of ID threads
> 1), then information about the received ID value is forwarded to the MI, along with the
SI identity, so that responses received at the MI can have their rid or bid properly restored at the SI. When a
multi-threaded master issues read or write transactions to different MI using different ID
values, the responses might be returned out-of-order, depending on when the responses are
received among the MI. By restoring the original ID value in the rid / bid of the response, the master device can
determine which transaction thread the response belongs to. When the core is configured with
STRATEGY==PERFORMANCE, all SI are configured as multi-threaded, with the number of threads
(reordering depth) set to 2Snn_AXI_ID_WIDTH, but no larger than 8.
An advanced mode of AXI Switch, called MI multi-threading, allows varying ID signals to
propagate to connected endpoint slave devices, allowing those slaves to respond out-of-order.
When enabled, a limited range of ID values generate at each endpoint MI of the core to
represent transactions originating with different IDs at an endpoint SI and/or originating
from different SI interfaces. The number of threads (ID values) supported depends on the
ID_WIDTH configured for the MI. The lifespan of a generated ID value ends
when all transactions belonging to the same ID thread complete at the MI; then that ID value
becomes available for reuse by a subsequent transaction thread arriving at the MI. There is no
correlation of ID values between write and read transaction on the same MI, or between
transactions issued among different MI.
AXI ID signals cannot be used in the system design to identify the master
originating an AXI transaction. Instead, AMD recommends using
the aruser and awuser signals to convey master
identification information, as needed.