For each MI that can be accessed by multiple SI, round-robin arbiters in the MI select the read command (AR channel) and write command (AW channel) to issue from the MI. A new read/write command can be issued each clock cycle, regardless of whether re-arbitrating a command from a different SI, or issuing a subsequent command from the same SI (back-to-back command arbitration).
For configurations with multiple MI, the STRATEGY parameter determines whether parallel pathways are implemented across the IP instance. When STRATEGY is BALANCED or PERFORMANCE, parallel pathways are implemented connected all SI to all MI, for all AXI channels, thus creating a full crossbar architecture. Commands targeting different MI from multiple SI can be arbitrated and issued concurrently. When STRATEGY is AREA, all SI fan in to a single pathway that fans out to all MI, which reduces the logic and routing resources. Consequently, for each of the AXI channels, only a single transfer can occur at a time.
For each SI that accesses multiple MI concurrently, round-robin arbiters in the
SI select among the R-channel and B-channel responses returned from the various MI. These
arbiters also support back-to-back transfers. In PERFORMANCE mode, the R-channel response
arbiters of multi-threaded SI support interleaving of read data beats among multiple MI, without
waiting for the end of the read burst (rlast) before re-arbitrating.