SI Parameters - SI Parameters - 1.0 English - PG453

AXI Switch v1.0 LogiCORE IP Product Guide (PG453)
Document ID
PG453
Release Date
2025-11-20
Version
1.0 English

Snn* parameters are hidden in the GUI for nn >= NUM SI.

Table 1. SI Parameters
User Parameter

(00<=nn <=15)

 Format Range Default Model Parameter Model Param Format Customization GUI Label, Description
Snn_AXI_PROTOCOL string AXI4, AXI3, AXI4LITE AXI4 C_S_AXI_PROTOCOL bitstring {C_NUM_ SI{int32}}, where int32 is:
  • 0=AXI4
  • 1=AXI3
  • 2=AXI4LITE
 Snn Protocol
Snn_AXI_ADDR_WIDTH Integer 1-64 32 C_S_AXI_ADDR_WIDTH bitstring {C_NUM_ SI{int32}} Snn Address Width
Snn_AXI_ID_WIDTH Integer 0-32 0 C_S_AXI_ID_WIDTH bitstring {C_NUM_ SI{int32}} Snn ID Width

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes all snn_axi_*id signals to become 1-bit wide and to be ignored/tied-off.
Snn_AXI_DATA_WIDTH Integer For AXI4, AXI3: 32, 64, 128, 256, 512, 1024

For AXI4-Lite: 32

 32 C_S_AXI_DATA_WIDTH bitstring {C_NUM_ SI{int32}} Snn Data Width
Snn_AXI_AWUSER_WIDTH Integer 0-512 0 C_S_AXI_AWUSER_WIDTH bitstring {C_NUM_ SI{int32}} Snn AWUSER Width

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the snn_axi_awuser signal to become 1-bit wide and to be ignored.
Snn_AXI_ARUSER_WIDTH Integer 0-512 0 C_S_AXI_ARUSER_WIDTH bitstring {C_NUM_ SI{int32}} Snn ARUSER Width

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the snn_axi_aruser signal to become 1-bit wide and to be ignored.
Snn_AXI_BUSER_WIDTH Integer 0-512 0 C_S_AXI_BUSER_WIDTH bitstring {C_NUM_ SI{int32}} Snn BUSER Width

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the snn_axi_buser signal to become 1-bit wide and to be tied-off.
Snn_AXI_RUSER_BITS_PER_BYTE Integer 0-4 0 C_S_AXI_RUSER_BITS_PER_BYTE bitstring {C_NUM_ SI{int32}} Snn RUSER Bits-per-Byte

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the snn_axi_ruser signal to become 1-bit wide and to be tied-off. Otherwise, signal width is Snn_AXI_RUSER_BITS_PER _BYTE * Snn_AXI_DATA_WIDTH/8.
Snn_AXI_WUSER_BITS_PER_BYTE Integer 0-4 0 C_S_AXI_WUSER_BITS_PER_BYTE bitstring {C_NUM_ SI{int32}} Snn WUSER Bits-per-Byte

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the snn_axi_wuser signal to become 1-bit wide and to be ignored. Otherwise, signal width is Snn_AXI_WUSER_BITS_PER_BYTE * Snn_AXI_DATA_WIDTH/8.
Snn_SUPPORTS_{READ, WRITE} Boolean false, true true C_S_SUPPORTS_{READ, WRITE} bitstring {C_NUM_ SI{int32}} (int32 = 0, 1) Snn Supports Read/Write

Setting SUPPORTS_READ== false causes all snn_axi_{ar,r}* ports to be disabled.

Setting SUPPORTS_WRITE== false causes all snn_axi_{aw,b,w}* ports to be disabled.
Snn_ACLK_RELATIONSHIP Signed Integer +1, 0, +2, +3, +4, +8, +16, -2, -3, -4, -8, -16

(Customization GUI labels: "Same", "Async", "2:1", "3:1", "4:1", "8:1", "16:1", "1:2", "1:3", "1:4", "1:8", "1:16")

 1 (Same) C_S_ACLK_RELATIONSHIP bitstring {C_NUM_ SI{signed32}} Snn Clock Relationship to aclk

0=Asynchronous clock conversion.

1=SI uses same clock domain as switchboard (aclk input).

+{2-16} = snn_axi_aclk: aclk ratio is n:1,

-{2-16} = snn_axi_aclk: aclk ratio is 1:|n|

When !=1, SI interface uses snn_axi_aclk input and internally-resynchronized aresetn.

When >1 or <-1, synchronous conversion is performed by transferring payload when both clocks have simultaneous rising edges. Clocks must therefore be generated from the same source and be edge-aligned (0 phase). 1

Snn_SUPPORTS_WRAP Boolean false, true true C_S_SUPPORTS_WRAP bitstring {C_NUM_ SI{int32}} (int32=0,1) Snn Supports WRAP bursts

If false, reduce area by omitting WRAP burst conversion logic.

When false, any in-bound WRAP transaction results in assertion of pc_asserted and pc_status outputs, accompanied by a DECERR response when NUM_MI > 1.

Disabled when PROTOCOL==AXI4LITE. 2

Snn_SUPPORTS_NARROW Boolean false, true true C_S_SUPPORTS_NARROW bitstring {C_NUM_ SI{int32}} (int32 = 0, 1) Snn Supports Narrow Bursts

If false, reduce area by omitting narrow burst conversion logic.

When false, any in-bound narrow burst (LEN>0 and SIZE< full dwidth) results in assertion of pc_asserted and pc_status outputs, accompanied by a DECERR response when NUM_MI > 1.

Disabled when PROTOCOL==AXI4LITE. 2

SAME_AS_S00 Boolean false, true false N/A - Make all SI same as S00

Setting true copies all above parameter values from S00 to all other SI and disables S01-S15 parameters.

Disabled when NUM_SI==1.
  1. Both "16:1" and "1:16" cannot be used in the same IP, as the Clock Wizard does not support that dynamic range of clock frequencies.
  2. Transactions appearing on any MI of AXI Switch (or AXI SmartConnect) are always INCR bursts and never use WRAP bursts.