Resets - Resets - 1.0 English - PG453

The AXI Switch IP has one active-Low reset input (aresetn). The reset input is internally resynchronized to each of the clock domains connected to the IP (except when the IP Is in ultra-low-area AXI4LITE mode).

If no soft reset is required beyond power-on, the aresetn pin can be tied high (inactive). All internal state logic is automatically initialized during powerup.

The IP also provides a reset output pin, for each enabled clock domain, as a convenience to connect to other logic in your design. This avoids having to instantiate other reset generator logic, such as the Processor System Reset IP (if your design already contains Processor System Reset instances, you do not need to change it). These reset outputs are always pulsed active following power-on regardless of whether the aresetn input is tied off.

The AXI Switch core de-asserts all valid and ready outputs during the power-on reset cycle and shortly after aresetn (if any) is sampled active, and for the duration of the aresetn pulse.

AXI protocol requires that all connected masters also de-assert all valid outputs during reset (until after aresetn is sampled inactive). Slaves must not assert response-channel valid outputs until after they receive a command from a master. It is also strongly recommended that slave IP de-assert their ready outputs until after reset. This avoids inadvertently signaling a transfer completion in case a connected IP recovers from reset during an earlier cycle and asserts its valid.

There is no requirement that the assertion or de-assertion of aresetn be observed during the same cycle or in any relative order among AXI Switch and its connected masters and slaves. It is, however, required that the cycles during which reset is applied to AXI Switch and all its connected masters and slaves overlap.

AXI Switch does not support independent reset domains. If any master or slave device connected to AXI Switch is reset, then all connected devices must be reset concurrently.