To simplify timing and increase system performance in a programmable device design, keep all inputs and outputs registered between the user application and the core. This means that all inputs and outputs from the user application should come from, or connect to, a flip-flop. While registering signals might not be possible for all paths, it simplifies timing analysis and makes it easier for the AMD tools to place and route the design.
When the core is configured to operate in ultra-low-area AXI4LITE mode (as indicated by
an INFO message in the log following customization), forward payload channels (AR, AW
and W) are implemented as wire-through paths fanning out to all MI. There are no timing
endpoints on forward channel MI payload outputs (all outputs other than
m*_axi_*valid). If pipelining of any of those pathways is needed,
AMD recommends instantiating AXI Register Slice IP. For more
information, see the
AXI
Register Slice IP LogiCORE IP Product Guide (PG373).