Port Descriptions - Port Descriptions - 1.0 English - PG453

AXI Switch v1.0 LogiCORE IP Product Guide (PG453)
Document ID
PG453
Release Date
2025-11-20
Version
1.0 English
Table 1. Port Descriptions
Signal Name

(00<=nn<=15)

 Enablement Description
aresetn Always Asynchronous active-Low global reset input. Internally resynchronized to the internal switchboard (aclk) clock domain and to any SI or MI clock domain different than aclk.

Might be tied High if no runtime reset is required.
aresetn_out Always Reset output (active-Low) of internal reset generator synchronized to the switchboard (aclk) clock domain.
snn_axi_aresetn_out, mnn_axi_aresetn_out Snn_ACLK_RELATIONSHIP != 1

Mnn_ACLK_RELATIONSHIP != 1

 Reset output (active-Low) of internal reset generators resynchronized to each configured SI/MI clock domain.
aclk Always Clock controlling the internal switchboard and any SI or MI configured to operate on the same clock domain as the switchboard (*ACLK_RELATIONSHIP==Same).
snn_axi_aclk, mnn_axi_aclk Snn_ACLK_RELATIONSHIP != 1

Mnn_ACLK_RELATIONSHIP != 1

 Clock controlling any SI or MI configured to operate on a different clock domain than the switchboard.
snn_axi_{ar, r}name where name is
  • valid
  • ready
  • addr
  • prot
  • data
  • resp
 nn < NUM_SI && Snn_SUPPORTS_READ SI AXI read channel signals used for all AXI protocols.
snn_axi_{aw, b, w}name where name is
  • valid
  • ready
  • addr
  • prot
  • data
  • strb
  • resp
 nn < NUM_SI && Snn_SUPPORTS_WRITE SI AXI write channel signals used for all AXI protocols.
snn_axi_wid nn < NUM_SI && Snn_AXI_PROTOCOL == AXI3 && Snn_SUPPORTS_WRITE SI AXI write channel signals used for AXI3 protocol.
snn_axi_{ar, r}name where name is not listed above nn < NUM_SI && Snn_AXI_PROTOCOL != AXI4LITE && Snn_SUPPORTS_READ SI AXI read channel signals used for AXI4 and AXI3 protocols.
snn_axi_{aw, b, w}name where name is not listed above nn < NUM_SI && Snn_AXI_PROTOCOL != AXI4LITE && Snn_SUPPORTS_WRITE SI AXI write channel signals used for AXI4 and AXI3 protocols.
mnn_axi_{ar, r}name where name is
  • valid
  • ready
  • addr
  • prot
  • data
  • resp
 nn < NUM_MI && Mnn_SUPPORTS_READ MI AXI read channel signals used for all AXI protocols.
mnn_axi_{aw, b, w}name where name is
  • valid
  • ready
  • addr
  • prot
  • data
  • strb
  • resp
 nn < NUM_MI && Mnn_SUPPORTS_WRITE MI AXI write channel signals used for all AXI protocols.
mnn_axi_wid nn < NUM_MI && Mnn_AXI_PROTOCOL == AXI3 && Mnn_SUPPORTS_WRITE MI AXI write channel signals used for AXI3 protocol.
mnn_axi_{ar, r}name where name is not listed above nn < NUM_MI && Mnn_AXI_PROTOCOL != AXI4LITE &&Mnn_SUPPORTS_READ MI AXI read channel signals used for AXI4 and AXI3 protocols.
mnn_axi_{aw, b, w} name where name is not listed above nn < NUM_MI && Mnn_AXI_PROTOCOL ! = AXI4LITE && Mnn_SUPPORTS_WRITE MI AXI write channel signals used for AXI4 and AXI3 protocols
pc_status Always Sideband output port indicating that an unexpected burst type transaction was received on a SI.

Bits [NUM_SI-1:0]: Indicates that the error occurred on the corresponding SI(s).

Bit [NUM_SI]: Asserted when the error is detected on the Read (AR) channel of the SI.

The following error conditions are trapped (but not distinguished):

  • Any FIXED burst
  • A WRAP burst when SUPPORTS_WRAP is disabled
  • A Narrow burst (a*len>0 and a*size<max) while SUPPORTS_NARROW is disabled

This signal remains sticky until reset. This signal is not synchronized to any particular clock domain.

In addition, an assertion is triggered for the first such read or write error occurring on each SI, which can be observed during simulation.
pc_asserted Always Sideband output port indicating the summary error condition for any unexpected burst type transaction received on any SI. This signal remains sticky until reset. This signal is not synchronized to a clock domain.