MI Parameters - MI Parameters - 1.0 English - PG453

AXI Switch v1.0 LogiCORE IP Product Guide (PG453)
Document ID
PG453
Release Date
2025-11-20
Version
1.0 English

Mnn* parameters are hidden in the GUI for nn >= NUM MI.

Table 1. MI Parameters
User Parameter

(00<=nn <=15)

 Format Range Default Model Parameter Model Param Format Customization GUI Label, Description
Mnn_AXI_PROTOCOL String AXI4, AXI3, AXI4LITE AXI4 C_M_AXI_PROTOCOL bitstring {C_NUM_ MI {int32}}, where int32 is:
  • 0=AXI4
  • 1=AXI3
  • 2=AXI4LITE
 Mnn Protocol
Mnn_AXI_ADDR _WIDTH Integer 1-64 32 C_M_AXI_ADDR _WIDTH bitstring {C_NUM_ MI{int32}} Mnn Address Width 1
Mnn_AXI_ID _WIDTH Integer 0-32 0 C_M_AXI_ID _WIDTH bitstring {C_NUM_ MI{int32}} Mnn ID Width

Disabled when MI_MULTITHREADING==false or PROTOCOL==AXI4LITE.

Setting to 0 causes all mnn_axi_*id signals to become 1-bit wide and ignored/tied-off.
Mnn_AXI_DATA _WIDTH Integer For AXI4, AXI3: 32, 64, 128, 256, 512, 1024

For AXI4-Lite: 32

 32 C_M_AXI_DATA_ WIDTH bitstring {C_NUM_ MI{int32}} Mnn Data Width
Mnn_AXI_AWUSER_WIDTH Integer 0-512 0 C_M_AXI_AWUSER_WIDTH bitstring {C_NUM_ MI{int32}} Mnn AWUSER Width

Disabled when PROTOCOL==AXI4LITE

Setting to 0 causes the mnn_axi_awuser signal to become 1-bit wide and tied-off.
Mnn_AXI_ARUSER_WIDTH Integer 0-512 0 C_M_AXI_ARUSER_WIDTH bitstring {C_NUM_ MI{int32}} Mnn ARUSER Width

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the mnn_axi_aruser signal to become 1-bit wide and tied-off.
Mnn_AXI_BUSER_WIDTH Integer 0-512 0 C_M_AXI_BUSER_WIDTH bitstring {C_NUM_ MI{int32}} Mnn BUSER Width

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the mnn_axi_buser signal to become 1-bit wide and ignored.
Mnn_AXI_RUSER_BITS_PER_BYTE Integer 0-4 0 C_M_AXI_RUSER_BITS_PER_BYTE bitstring {C_NUM_ MI{int32}} Mnn RUSER Bits-per-Byte

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the mnn_axi_ruser signal to become 1-bit wide and to be ignored. Otherwise, signal width is Mnn_AXI_RUSER_BITS _PER_BYTE * Mnn_AXI_DATA_WIDTH/8.
Mnn_AXI_WUSER_BITS_PER_BYTE Integer 0-4 0 C_M_AXI_WUSER_BITS_PER_BYTE bitstring {C_NUM_ MI{int32}} Mnn WUSER Bits-per-Byte

Disabled when PROTOCOL==AXI4LITE.

Setting to 0 causes the mnn_axi_wuser signal to become 1-bit wide and tied-off. Otherwise, signal width is Mnn_AXI_WUSER_BITS _PER_BYTE * Mnn_AXI_DATA_WIDTH/8.
Mnn_SUPPORTS_{READ,WRITE} Boolean false, true true C_M_SUPPORTS_{READ,WRITE} bitstring{C_NUM_MI{int32}}(int32 = 0,1) Mnn

Supports Read/Write Setting SUPPORTS_READ==false causes all mnn_axi_{ar,r}* ports to be disabled.

When SUPPORTS_WRITE==false, all mnn_axi{aw,b,w}* ports are disabled.
Mnn_ACLK_RELATIONSHIP Signed Integer

+1, 0, +2, +3, +4, +8, +16, -2, -3, -4, -8, -16

(Customization GUI labels: "Same", "Async", "2:1", "3:1", "4:1", "8:1", "16:1", "1:2", "1:3", "1:4", "1:8", "1:16")

 1 (Same) C_M_ACLK_RELATIONSHIP bitstring {C_NUM_ MI{signed32}} Mnn Clock Relationship to aclk

0=Asynchronous clock conversion.

1=MI uses same clock domain as switchboard (aclk input).

+{2-16} = mnn_axi_aclk: aclk ratio is n:1,

-{2-16} = mnn_axi_aclk: aclk ratio is 1:|n|

When !=1, MI interface uses mnn_axi_aclk input and internally-resynchronized aresetn. 2

When >1 or <-1, synchronous conversion is performed by transferring payload when both clocks have simultaneous rising edges. Clocks must therefore be generated from the same source and be edge-aligned (0 phase).

Disabled when NUM_SI=1 and NUM_MI=1; use S00_ACLK_RELATIONSHIP instead.
SAME_AS_M00 Boolean false, true false n/a - Make all MI same as M00

Setting true copies all above parameter values from M00 to all other MI and disables M01-M15 parameters.

Disabled when NUM_MI==1.
  1. When Mnn_AXI_ADDR_WIDTH != Snn_AXI_ADDR_WIDTH, truncation/padding of the out-bound address occurs.
  2. Both "16:1" and "1:16" cannot be used in the same IP, as the Clock Wizard does not support that dynamic range of clock frequencies.