The AXI Switch IP connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI Switch is a RTL-based IP. Once customized, the generated component wrapper is intended to be instantiated into a RTL design. The AXI Switch can also be included in RTL modules to be packaged into custom IP.
The AXI Switch IP replicates much of the same functionality as the AXI SmartConnect IP. For more information, see the SmartConnect LogiCORE IP Product Guide (PG247). However, AXI Switch is available only from the Vivado IP catalog, whereas Smartconnect is available only from the IP integrator IP catalog for use in IP integrator block diagrams. All aspects of AXI Switch IP configuration are specified manually via its Customization GUI (or by setting user-parameter values in the Tcl Console), whereas the majority of Smartconnect's configuration is automatically derived from the surrounding logic in the Block Diagram and from the IP integrator Address Editor.
The AXI Switch IP supports all FPGA families.