Transfers on all five AXI channels are buffered on both the SI and MI-sides of the central switching plane to support high throughput and reduce throttling. For AXI4 and AXI3 interfaces, buffers on the SI and MI sides for each channel are implemented using 32-deep distributed RAM FIFOs. The depths of buffering for various channels vary among STRATEGY settings:
| Setting | Area | Balanced | Performance |
|---|---|---|---|
| SI-side R and W channel data FIFO depth | 1 (register) | 32 (1 LUT-RAM) | 512 (1 BRAM) |
| MI-side R and W channel data FIFO depth | 1 (register) | 32 (1 LUT-RAM) | 32 (1 LUT-RAM) |
| AR, AW, and B channel FIFO depth | 1 (register) | 32 (1 LUT-RAM) | 32 (1 LUT-RAM) |