Global Parameters - Global Parameters - 1.0 English - PG453

AXI Switch v1.0 LogiCORE IP Product Guide (PG453)
Document ID
PG453
Release Date
2025-11-20
Version
1.0 English
Table 1. Global Parameters
User Parameter Format Range Default Model Parameter Model Param Format Customization GUI Label, Description
NUM_SI Integer 1-16 1 C_NUM_SI Integer Number of slave interfaces
NUM_MI Integer 1-16 1 C_NUM_MI Integer Number of master interfaces
STRATEGY String PERFORMANCE, BALANCED, AREA BALANCED C_STRATEGY Integer:
  • 0=AREA
  • 1=BALANCED
  • 2=PERFORMANCE
 Area/Performance Tradeoff

Selects a predefined formula for various internal optimization settings. Refer to Table 2 and Table 1.
CDC_ENABLE Boolean false, true false N/A   Enable multiple clock domains.

When true, the Snn_ACLK_RELATIONSHIP and Mnn_ACLK_RELATIONSHIP parameters become visible.
MI_MULTITHREADING Boolean false, true false N/A  

Enable ID signal values on MI.

When true, Mnn_AXI_ID_WIDTH parameters become visible.

Disabled when STRATEGY==AREA.
Table 2. Global Parameters - Predefined Optimization Settings Selected by STRATEGY
Setting Area Balanced Performance
Maximum number of outstanding read or write transactions 1 32 32
Internal Switchboard Data Width

min(max(SI_Dwidth), max (MI_Dwidth))

 max (MI_Dwidth) max(max(SI_Dwidth), max(MI_Dwidth))
SI-side data FIFO depth 1 (register slice) 32 (1 LUT-RAM) 512 (1 BRAM)
MI-side data FIFO depth 1 (register slice) 32 (1 LUT-RAM) 32 (1 LUT-RAM)
Number of ID threads (reordering depth) 1 1 (single-ordering) min(8, 2ID_WIDTH)