- Up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI)
per instance.
- Instances of AXI Switch can be cascaded to interconnect a larger number of
masters/slaves or for organizing the interconnect topology.
- AXI Protocol compliant. Each SI and MI of AXI Switch can be
configured to be AXI3, AXI4, or AXI4-Lite.
- Transactions between interfaces of different protocol types
are automatically converted by AXI Switch.
- Burst transactions are automatically split, as required, to
remain AXI compliant.
- Interface Data Widths:
-
AXI4 and AXI3: 32, 64, 128, 256, 512, or 1024 bits.
-
AXI4-Lite: 32 bits.
- Transactions between interfaces of different data widths are
automatically converted by AXI Switch.
- Supports Multiple Clock Domains:
- Transactions between interfaces in different clock domains are automatically
converted by AXI Switch.
- Both asynchronous and synchronous (edge-aligned) conversions are supported,
per interface.
- Address Width: Up to 64 bits.
- AXI Switch decodes up to 64 total address range
segments.
- Supports address ranges beginning and ending on any 4-byte word alignment
(non-power-of-2 addressing)
- User defined signals up to 512 bits wide per channel.
- User signals on any AXI channel are propagated regardless of internal
transaction conversions.
- Supports read-only and write-only SI and MI.
- Supports multiple outstanding transactions:
- Supports connected masters with multiple reordering depth (ID threads).
- Supports write response reordering, read data reordering, and read data
interleaving.
- Multi-Threaded traffic (masters issuing multiple ID threads)
is supported regardless of internal transaction conversions, including data
width conversion and transaction splitting.
- Optionally produces varying ID signals at the MI to allow connected slaves
to respond out-of-order (MI multi-threading).
- Single-Slave per ID method of cyclic dependency (deadlock)
avoidance.
- For each ID thread issued by a connected master, the AXI Switch allows one
or more outstanding transactions to only one slave device for writes and one
slave device for reads, at a time.
- Multiple parallel pathways along all AXI channels when connected to multiple masters
and multiple slaves:
- Each AXI channel has independent destination-side arbitration. Transfers
from two or more source endpoints to separate destination endpoints can
occur concurrently, for any AXI channel.
- Round-Robin arbitration for each of the AW, AR, R, and B
channels. W-channel transfers follow the same order as AW-channel
arbitration, per AXI protocol rules.
- Supports back-to-back transfers (100% duty cycle) on any AXI
channel.
- Single data-beat transactions can traverse the AXI Switch at the same
bandwidth as multi-beat bursts.
- Supports TrustZone security for each connected slave:
- If configured as a secure address segment, only secure AXI accesses are
permitted according to the AXI arprot or awprot signal.
- Any non-secure accesses are blocked and the AXI Switch core issues a DECERR
response at the SI.
- Internally resynchronized reset:
- One
aresetn input per IP.