Example Design - Example Design - 1.0 English - PG453

This chapter contains information about the example design provided in the Vivado Design Suite. The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown below. This includes clocking wizard, AXI master and slave modules.

The example design generates N number of master interfaces and M number of slave interfaces based on the configuration of 'N' SI interfaces and 'M' MI interfaces of the DUT.

clk_wiz

Clocking wizard instances are used to generate the clocks required for the IP. It generates aclk and other master and slave clocks based on the configuration.

Master Instance

Depending on the protocol configuration of each SI interface of the DUT, the corresponding master interface generates AXI4-Lite/AXI3/AXI4 traffic. When all the transactions generated by the master instance are completed with response, the instance generates a done signal. When all the master instances generate done, the test case finishes.

Slave Instance

Depending on the protocol configuration of each MI interface of the DUT, the corresponding master accepts AXI4-Lite/AXI3/AXI4 traffic from the DUT and generates a response after the transaction is finished.

The test starts soon after the reset is released and clocking wizards are locked. The Done pin is asserted High after all the transactions are completed on each master instance.