When there are more than one SI on which multiple outstanding transactions can be issued, and there are more than one MI that can queue multiple transactions, there is a potential cyclic dependency (deadlock) risk.
The AXI Switch uses the Single Slave per ID method to avoid deadlock. The Single Slave per ID method imposes the restriction that each ID thread received at each SI (from each master device) can have outstanding transactions (in each of the write and read directions) to only one target MI at a time. However, each MI is still permitted to issue multiple outstanding transactions originating from multiple SI.
As well as preventing deadlock, the Single Slave per ID rule also guarantees in-order completion of all Write transactions belonging to the same ID-thread, even if different MI are targeted in successive transactions. For example, a master device writes to a direct memory access (DMA) descriptor in memory, then writes (using the same thread-ID) to a control register in a DMA engine which subsequently reads that descriptor. Because AXI Switch does not allow the second Write to propagate to the DMA slave device until the first Write completes (Write response received from the memory controller), there is no risk that the DMA reads stale descriptor data from memory. Each master device is therefore guaranteed in-order completion of transactions to various slave devices, in the same direction, and on the same ID thread. Therefore, under those conditions, master devices do not need to condition subsequent Write transactions on receiving Write responses for prior transactions.