An AXI4 or AXI3 SI can receive any protocol-compliant transaction and send it through the AXI Switch to an AXI4-Lite MI. AXI Switch converts AXI4/AXI3 multi-beat bursts into a sequence of single-beat transactions for AXI4-Lite MI.
For write transactions, any W-channel data beat in which all wstrb bits are
deasserted (null data beat), propagation to the MI is suppressed. However, if all data beats of
the transaction are null beats, one write transaction is issued on the MI (at the original
starting address) with all wstrb bits deasserted, and the write-response
received on the B-channel of the MI is propagated back to the SI.