Constraining the Core - Constraining the Core - 1.0 English - PG453

For each SI/MI configured to operate asynchronously to aclk, the core automatically generates a set_false_path constraint (scoped to the IP instance) to avoid timing violations across CDC pathways. For each SI/MI configured to operate at a specified synchronous relationship to aclk, no timing constraint is generated and no timing constraint should be specified, as all CDC pathways are expected to meet the timing requirements for both applicable clocks. In addition, the core automatically generates a set_false_path constraint to cover the internal resynchronization of each aresetn input pin, except when configured in ultra-low-area mode.