Comparison to AXI SmartConnect - Comparison to AXI SmartConnect - 1.0 English - PG453

This section highlights the features that differ between AXI Switch v1.0 and AXI SmartConnect v1.0.

• You must manually select the desired Performance/Area tradeoff. STRATEGY does not change automatically based on SI/MI Protocol selections.
• AXI Switch does not support more than 16 MI per instance.
• When multiple instances of AXI Switch are cascaded, downstream instances do not inherit any metadata information or partial results from upstream instances.
  • Each instance with multiple MI performs its own address decode to determine the targeted MI.
  • Each instance with multiple MI performs its own deadlock avoidance.
  • Each instance that performs downsizing or protocol conversion performs its own transaction splitting, as needed.
  • You can safely disable SUPPORTS_WRAP and SUPPORTS_NARROW for cascaded SI on downstream instances of the AXI Switch to avoid unnecessary duplication of burst conversion logic.
• AXI Switch does not provide built-in boundary register slices on each SI/MI. Pipelining of critical paths that span SI/MI connections can be addressed by instantiating AXI Register Slice IP. For more information, see the AXI Register Slice IP LogiCORE IP Product Guide (PG373).
• AXI Switch enables a separate clock input pin for each SI and MI interface that is configured to be in a different clock domain than the internal switchboard.
  • The AXI Switch functionality in terms of clocking is determined in strict accordance with the user parameters and does not depend on clock metadata (FREQ_HZ) or clock constraints (create_clock).
• AXI Switch supports a maximum of 16 address segments per MI and a total maximum of 64 segments across the whole instance.
• AXI Switch does not support 64-bit AXI4-Lite interfaces.
• AXI Switch restricts R/WUSER signal width to an integer number of bits per byte of data-width.
• AXI Switch does not support the aclken input.
• AXI Switch performs address decode only when NUM_MI>1; it performs no address range checking when NUM_MI=1.
• AXI Switch does not support sparse connectivity. Pathways are implemented between all physically-enabled SI and MI. Endpoint slave access restrictions cannot be specified on a per-SI basis.
• AXI Switch uses the same address map for all SI. It does not support any variation of address apertures across SI.
• AXI Switch does not support the "Packet-mode" data buffering (PKT_W/R_THR) advanced feature of SmartConnect.
• AXI Switch does not support the "Limit Read/Write Length" (LIM_R/W_LEN) advanced feature of SmartConnect.
• AXI Switch does not support SLR crossing pipelines.