By default, all interfaces on the AXI Switch operate in the same clock domain
as the central switchboard, and the clock is received on the aclk input pin
of the IP. Each SI and MI can be configured to operate in a different clock domain than the
switchboard (aclk). For each SI or MI that is configured to operate in a
different domain than aclk, an interface-specific clock input pin is enabled
on the IP to connect the appropriate clock. When payload is transferred along any AXI channel
between interfaces belonging to different clock domains, clock conversion logic is
automatically inserted along the pathway.
When an interface is configured for asynchronous operation, the clock domain
crossings are performed by the existing SI-side or MI-side payload FIFO for each channel,
which are reconfigured in dual-clock mode. Dual-clock FIFOs are designed to internally
resynchronize their write and read clock domains, regardless of their phase or frequency
relationship. The FIFOs are capable of supporting back-to-back transfers on the slower of its
interfaces, but introduce resynchronization latency. In asynchronous mode, the IP
automatically generates appropriate set_false_path timing
constraints to cover all resynchronization paths.
The AXI Switch IP is also capable of performing synchronous clock conversion
for a limited set of integer clock ratios of the SI or MI clock with respect to aclk:
- 2:1
- 3:1
- 4:1
- 8:1
- 16:1
- 1:2
- 1:3
- 1:4
- 1:8
- 1:16
Synchronous clock conversion does not need to resynchronize FIFO read/write operations, and so avoids additional latency and does not generate set_false_path timing constraints. The synchronous clock conversion logic automatically detects cycles of the faster clock for which there are simultaneous active edges of the slower clock, transferring payload between the clock domains during those cycles.
The SI/MI clock waveform must adhere to the selected ratio to the aclk
frequency. Furthermore, the SI/MI clock must be generated by the same clock source (Clock
Wizard) as aclk, and the clocks must be edge-aligned (both have 0
phase-shift). Unlike AXI Smartconnect, which enables sync conversion only for those clocks
that are known to meet these requirements (according to IP integrator metadata), the AXI
Switch IP and Vivado tools provide no validation of these rules for your clock
sources. Failure to follow these rules can result in functional failure of your hardware
design. If any functional failure is observed involving synchronous ACLK_RELATIONSHIP,
reverting to ASYNC can help isolate and/or alleviate the problem.