When configured with more than one MI, the AXI Switch core must determine which MI is the target of each transaction by decoding the address of each AW and AR channel transfer received at an SI. This address decode involves only those upper order address bits needed to distinguish between MI, and ignores lower-order bits that might be used to distinguish locations within the connected slave device.
The entire address value received from the SI is presented to the MI (adjusting for differences in Address Width) and made available to the slave device. It is visible to any connected monitors, even though the high-order address bits are typically not reused by the slave device.
In some cases, there might be multiple, possibly disjointed, address ranges that define when a single MI is accessed. The address decode logic in the AXI Switch core includes the multiple ranges that determine the selection of each MI.
Whenever a transaction address received on the SI does not match any of the ranges being decoded by the AXI Switch, the transaction is trapped and handled by a decode error module within the core. The core generates a protocol-compliant response back to the originating SI with the decode error (DECERR) response code. The offending transaction is not observed on any MI.
When configured with one MI, the AXI Switch core performs no address decode or
range checking. All valid transactions received on any SI are propagated to the MI. In the N×1
configuration, the IP does not support read/write access restrictions or TrustZone security.
Also, when STRATEGY=AREA is selected,
any unsupported FIXED, WRAP, or Narrow bursts that might be erroneously received on any SI
does not result in a DECERR response but is still indicated on the pc_status
output signal.
AXI Switch performs no address re-mapping. The address segment(s) corresponding to each MI are seen the same way across all SI (flat address space). SI with an address width less than the full address width spanned by all accessible MI, can only access those address segments mapped at the low end of the address space.