AXI Switch Core Limitations - AXI Switch Core Limitations - 1.0 English - PG453

AXI Switch v1.0 LogiCORE IP Product Guide (PG453)
Document ID
PG453
Release Date
2025-11-20
Version
1.0 English
  • AXI Switch is not intended for use in IP integrator (IPI) Block Diagram designs.
    • AXI Switch does not participate in any IP integrator automation or metadata propagation.
    • AXI Switch inherits no information from the IP integrator Address Editor. All address decode ranges must be expressed manually by setting its user parameters.
    • You must manually select the desired Performance/Area tradeoff (STRATEGY).
  • AXI Switch unconditionally packs all multi-beat bursts to fill the interface data-width.

    AXI Switch Slave Interfaces (SI) accept narrow bursts, in which the arsize or awsize signal indicates data units which are smaller than the interface data-width. But such bursts are always propagated through the AXI Switch and its Master Interfaces (MI) fully packed. The modifiable bit of the AXI arcache or awcache signal does not prevent packing.

    When a single-beat transaction (arlen = 0 or awlen = 0) is received and the arsize or awsize signal indicate a data unit smaller than the data-width of the targeted MI, the narrow size of the single-beat transaction is preserved and propagated to the MI, so that the range of address locations originally specified by the master are not exceeded.

  • For each SI/MI interface on each AXI Switch IP instance, you must manually configure interface properties for compatibility with connected master/slave endpoints or connected cascaded AXI Switch instances.
  • AXI Switch converts all WRAP type bursts into INCR type. AXI Switch SI accept all protocol-compliant WRAP bursts, beginning at any target address. But such bursts are always converted to a single INCR burst or a series of single-beat transactions beginning at the wrap address.
  • AXI Switch does not support FIXED type bursts. Any FIXED burst transaction received at the AXI Switch SI is regarded as a decode error.
  • AXI ID signals cannot be used in the system to identify the master originating an AXI transaction. Instead, AMD recommends using the aruser and awuser signals to convey master identification information, as needed.
  • The AXI Switch core does not support discontinued AXI3 features:
    • Atomic locked transactions: This feature was retracted by the AXI4 protocol. A locked transaction is changed to a non-locked transaction and propagated by the MI.
    • Write interleaving: This feature was retracted by AXI4 protocol. AXI3 master devices must be configured as if connected to a slave with a write interleaving depth of one.
  • The AXI Switch core does not support exclusive access transactions.
  • All arbitration on all AXI channels is round-robin.
  • AXI4 Quality of Service (arqos and awqos) signals do not influence arbitration priority. QoS signals are propagated from SI to MI.
  • AXI Switch neither propagates nor generates the AXI4 arregion or awregion signal.
  • AXI Switch does not support independent reset domains. If any master or slave device connected to AXI Switch is reset, then all connected devices must be reset concurrently.
  • AXI Switch does not propagate the AXI Low power interface (C-channel) signals.
  • AXI Switch does not time out if the destination of any AXI channel transfer stalls indefinitely. All connected AXI slaves must respond to all received transactions, as required by AXI protocol.
  • AXI Switch provides no address remapping.
  • AXI Switch does not include conversion or bridging to non-AXI protocols, such as APB.
  • AXI Switch does not support the AXI Coherency Extensions (ACE) protocol nor AMBA AXI5 protocol.